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SPC564A80L7 - 32-bit MCU

Download the SPC564A80L7 datasheet PDF. This datasheet also covers the SPC564A74B4 variant, as both devices belong to the same 32-bit mcu family and are provided as variant models within a single manufacturer datasheet.

Description

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Features

  • 150 MHz e200z4 Power Architecture® core.
  • Variable length instruction encoding (VLE).
  • Superscalar architecture with 2 execution units.
  • Up to 2 integer or floating point instructions per cycle.
  • Up to 4 multiply and accumulate operations per cycle.
  • Memory organization.
  • 4 MB on-chip flash memory with ECC and Read While Write (RWW).
  • 192 KB on-chip RAM with standby functionality (32 KB) and ECC.
  • 8 KB instruction cache (with lin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SPC564A74B4-STMicroelectronics.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by STMicroelectronics

Part Number Description
SPC564A80B4 32-bit MCU
SPC564A74B4 32-bit MCU
SPC564A74L7 32-bit MCU
SPC564B64L7 32-bit MCU
SPC564B64L8 32-bit MCU

Full PDF Text Transcription

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SPC564A74B4, SPC564A74L7, SPC564A80B4, SPC564A80L7 32-bit MCU family built on the embedded Power Architecture® Features ■ 150 MHz e200z4 Power Architecture® core – Variable length instruction encoding (VLE) – Superscalar architecture with 2 execution units – Up to 2 integer or floating point instructions per cycle – Up to 4 multiply and accumulate operations per cycle ■ Memory organization – 4 MB on-chip flash memory with ECC and Read While Write (RWW) – 192 KB on-chip RAM with standby functionality (32 KB) and ECC – 8 KB instruction cache (with line locking), configurable as 2- or 4-way – 14 + 3 KB eTPU code and data RAM – 5  4 crossbar switch (XBAR) – 24-entry MMU – External Bus Interface (EBI) with slave and master port ■ Fail Safe Protection – 16-entry Memory Protection Unit (MPU) –
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