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PSD835G2V - Flash PSD

Description

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Features

  • Flash in-system programmable (ISP) peripheral for 8-bit MCUs Dual bank Flash memories.
  • 4 Mbits of Primary Flash memory (8 uniform sectors, 64 Kbyte).
  • 256 Kbits of secondary Flash memory with 4 sectors.
  • Concurrent operation: READ from one memory while erasing and writing the other 64 Kbit of battery-backed SRAM 52 reconfigurable I/O ports Enhanced JTAG serial port PLD with macrocells.
  • Over 3000 gates of PLD: CPLD and DPLD.
  • CPLD with 16 output ma.

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Full PDF Text Transcription

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PSD835G2V Flash PSD, 3 V supply, for 8-bit MCUs 4 Mbit + 256 Kbit dual Flash memories and 64 Kbit SRAM Features ■ Flash in-system programmable (ISP) peripheral for 8-bit MCUs Dual bank Flash memories – 4 Mbits of Primary Flash memory (8 uniform sectors, 64 Kbyte) – 256 Kbits of secondary Flash memory with 4 sectors – Concurrent operation: READ from one memory while erasing and writing the other 64 Kbit of battery-backed SRAM 52 reconfigurable I/O ports Enhanced JTAG serial port PLD with macrocells – Over 3000 gates of PLD: CPLD and DPLD – CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs) – DPLD - user defined internal chip select decoding 52 individually configurable I/O port pins They can be used for the following functions: – MCU I/Os – PLD I/Os – Latched MCU address
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