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ISB35666 - HCMOS STRUCTURED ARRAY

Download the ISB35666 datasheet PDF. This datasheet also covers the ISB variant, as both devices belong to the same hcmos structured array family and are provided as variant models within a single manufacturer datasheet.

General Description

The ISB35000 array series uses a high performance, low voltage, triple level metal, HCMOS 0.5 micron process to achieve sub-nanosecond internal speeds while offering very low power dissipation and high noise immunity.

The potential total gate count ranges above 1 million equivalent usable gates.

Key Features

  • 0.5 micron triple layer metal HCMOS process featuring retrograde well technology, low resistance salicided active areas, polysilicide gates and thin metal oxide. 3.3 V optimized transistor with 5 V I/O interface capability 2 - input NAND delay of 0.210 ns (typ) with fanout = 2. Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS. High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike suppression and impedance matching. Metallised generators to su.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ISB-3500.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by STMicroelectronics

Part Number Description
ISB35000 HCMOS STRUCTURED ARRAY
ISB35083 HCMOS STRUCTURED ARRAY
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ISB35166 HCMOS STRUCTURED ARRAY
ISB35208 HCMOS STRUCTURED ARRAY

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
ISB35000 SERIES HCMOS STRUCTURED ARRAY PRELIMINARY DATA FEATURES 0.5 micron triple layer metal HCMOS process featuring retrograde well technology, low resistance salicided active areas, polysilicide gates and thin metal oxide. 3.3 V optimized transistor with 5 V I/O interface capability 2 - input NAND delay of 0.210 ns (typ) with fanout = 2. Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS. High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike suppression and impedance matching. Metallised generators to support SPRAM and DPRAM, plus an extensive embedded function library. Combines Standard Cell Features with Sea of Gates time to market. Table 1.