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HCC4096B - GATE J-K MASTER-SLAVE FLIP-FLOPS

Description

inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse.

SET and RESET inputs (active high) are provided for asynchronous operation.

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Full PDF Text Transcription

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HCC/HCF4095B HCC/HCF4096B GATE J-K MASTER-SLAVE FLIP-FLOPS . . . . . . . 16 MHz TOGGLE RATE (typ.) AT VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT SPECIFIED TO 20v FOR HCC DEVICE 5V, 10V AND 15V PARAMETRIC RATINGS INPUT CURRENTOF 100 nA AT 18V AND 25oC FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No 13 A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES” inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation.
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