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ST26C32A - CMOS QUAD 3-STATE DIFFERENTIAL LINE RECEIVER

General Description

The ST26C32A is a quad differential line receiver designed to meet the RS-422, RS-423 standards for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS.

Key Features

  • internal pull-up and pull-down resistors which prevent output oscillation on unused channels. The ST26C32A provides an enable and disable function to all four receivers and features 3-STATE output with 6mA source and sink capability.

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Full PDF Text Transcription (Reference)

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ST26C32A CMOS QUAD TRI-STATE DIFFERENTIAL LINE RECEIVER s s s s s s s s CMOS DESIGN FOR LOW POWER ±0.2V SENSITIVITY OVER INPUT COMMON MODE VOLTAGE RANGE TYPICAL PROPAGATION DELAY: 19ns TYPICAL INPUT HYSTERESIS: 60mV INPUT WILL NOT LOAD LINE WHEN VCC=0V MEETS THE REQUIREMENTS OF EIA STANDARD RS-422, RS-423 3-STATE OUTPUTS FOR CONNECTION TO SYSTEM BUSES AVAILABLE IN SURFACE MOUNT DIP SOP DESCRIPTION The ST26C32A is a quad differential line receiver designed to meet the RS-422, RS-423 standards for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS. The ST26C32A has an input sensitivity of 200mV over the common mode input voltage range of ±7V.