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M54HC280 - 9 BIT PARITY GENERATOR

General Description

The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology.

It has the same high speed performance of LSTTL combined with true CMOS low consumption.

It is composed of nine data inputs (A to I) and odd/even parity outputs (Σ ODD and Σ EVEN).

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Full PDF Text Transcription for M54HC280 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for M54HC280. For precise diagrams, tables, and layout, please refer to the original PDF.

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M54HC280 M74HC280 9 BIT PARITY GENERATOR . . . . . . . . HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C 6 V HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS280 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC280F1R M74HC280M1R M74HC280B1R M74HC280C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology.