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M48Z128Y - 1 Mbit (128 Kbit x 8) ZEROPOWER SRAM

General Description

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Key Features

  • Integrated, ultra low power SRAM, power-fail control circuit, and battery.
  • Conventional SRAM operation; unlimited )WRITE cycles t(s.
  • 10 years of data retention in the absence of cpower du.
  • Battery internally isolated until power is first roapplied P.
  • Automatic power-fail chip deselect and WRITE protection lete.
  • WRITE protect voltages: o(VPFD = power-fail deselect voltage) s.
  • M48Z128: VCC = 4.75 to 5.5 V; b4.5 V ≤ VPFD ≤ 4.75 V O.
  • M48Z128Y: VCC = 4.5.

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Full PDF Text Transcription for M48Z128Y (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for M48Z128Y. For precise diagrams, tables, and layout, please refer to the original PDF.

M48Z128 M48Z128Y 5.0 V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM Not recommended for new design Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and ...

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s ■ Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ Conventional SRAM operation; unlimited )WRITE cycles t(s■ 10 years of data retention in the absence of cpower du■ Battery internally isolated until power is first roapplied P■ Automatic power-fail chip deselect and WRITE protection lete■ WRITE protect voltages: o(VPFD = power-fail deselect voltage) s– M48Z128: VCC = 4.75 to 5.5 V; b4.5 V ≤ VPFD ≤ 4.75 V O– M48Z128Y: VCC = 4.5 to 5.5 V; ) -4.2 V ≤ VPFD ≤ 4.