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S71WS512N - Migrating from the S71WS512N to the S71WS512P

Description

There are also a few hardware changes required for the migration.

Since the entire S29WS512P is addressed with a single chip select, address line A24 has to be connected.

Note that some systems may require a pull down resistor on A24.

Features

  • between the two flash device cores. Table 1.1 Comparison of Key Features Futures Technology Process Rule VCC VIO (VCCQ) Max Density Configuration Register Sector Architecture Bank Architecture Bank Size Boot Option Common Flash Interface (CFI) Simultaneous Read/Write Asynchronous Read Mode Page Mode Read Page Size Synchronous (Burst) Read Mode Burst Frequency Burst Length Single Word / Write Buffer Program Write Buffer Size Program Suspend / Program Resume Sector Erase / Chip Erase Erase Suspend.

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S71WS512N Stacked Multi-Chip Product (MCP)
S71WS512NX0 Stacked Multi-Chip Product (MCP)
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com S71WS512N to S71WS512P Migrating from the S71WS512N to the S71WS512P Application Note by Daisuke Nakata 1. Introduction Migrating from the S71WS512N to the monolithic S71WS512P is a simple process; however, the user should be aware of a few differences between these two parts. These differences are the result of the S71WS512N using two S29WS256N die in series while the S71WS512P uses a single S29WS512P configuration. This application note describes these differences in detail so users currently using the S71WS512N configuration can plan ahead and include the necessary software to ensure a smooth migration to the S71WS512P. Both software and hardware considerations are covered. Table 1.1 shows a comparison of the key features between the two flash device cores.
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