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RT9173D - Peak 3A Sink/Source Bus Termination Regulator

Datasheet Summary

Description

The RT9173D is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc.

devices requirements.

Features

  • include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The RT9173D are available in the SOP-8 (Exposed Pad) surface mount packages. Ordering Information RT9173D Package Type SP : SOP-8 (Exposed Pad-Option 1) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Note : Richtek products are :  RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.  Suitab.

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Datasheet Details

Part number RT9173D
Manufacturer Richtek
File Size 288.48 KB
Description Peak 3A Sink/Source Bus Termination Regulator
Datasheet download datasheet RT9173D Datasheet
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Full PDF Text Transcription

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® RT9173D Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator General Description The RT9173D is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing continuous 2A or up to 3A transient peak current while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the REFEN pin voltage.
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