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RC21008A - VersaClock 7 Programmable Clock Generator

Datasheet Summary

Description

RCxx012A 7 1.3 Pin Assignments RCxx008A

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RCxx008A

Features

  • 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz).
  • PCIe® Gen6 Common Clock (CC) 27fs RMS.
  • PCIe SRIS and SRNS support.
  • 1kHz to 650MHz LVDS/LP-HCSL outputs 008 A/012A XIN_REFIN X XOUT_REFINb O CLKIN0_GPI0 CLKIN0b_GPI1 CLKIN1_GPI2 CLKIN1b_GPI3 APL L GPIO[4:0] SCL_SCLK SDA_nCS GPIO Ser ial Por t OTP Use r Cfgs Registe rs A. IOD0 is n/a on 008 devices MUX MUX.
  • 1kHz to 200MHz LVCMOS outputs.
  • Simple AC-coupling to LVPECL and CML.
  • LP-HCSL integrates 100 o.

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Datasheet preview – RC21008A

Datasheet Details

Part number RC21008A
Manufacturer Renesas
File Size 1.90 MB
Description VersaClock 7 Programmable Clock Generator
Datasheet download datasheet RC21008A Datasheet
Additional preview pages of the RC21008A datasheet.
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Full PDF Text Transcription

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RC210xxA VersaClock 7 Programmable Clock Generator Family Datasheet The RC210xxA (RC21012A and RC21008A) are high-performance programmable clock generators for compute, data-communications, and industrial applications. Applications ▪ High-performance computing ▪ Data center accelerators ▪ Enterprise storage ▪ Switches and routers ▪ Industrial Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs 008 A/012A XIN_REFIN X XOUT_REFINb O CLKIN0_GPI0 CLKIN0b_GPI1 CLKIN1_GPI2 CLKIN1b_GPI3 APL L GPIO[4:0] SCL_SCLK SDA_nCS GPIO Ser ial Por t OTP Use r Cfgs Registe rs A.
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