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R5F51115AGFM - 32 MHz 32-bit RX MCUs

Description

Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Ba

Features

  • 32-bit RX CPU core.
  • 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz.
  • Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations.
  • Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle).
  • Fast interrupt.
  • CISC Harvard architecture with five-stage pipeline.
  • Variable-length instruction format, ultra-compact code.
  • On-chip debuggi.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Datasheet RX111 Group Renesas MCUs R01DS0190EJ0100 Rev.1.00 Jun 19, 2013 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, USB 2.0 full-speed host/function/OTG, up to 6 comms channels, 12-bit A/D, 8-bit D/A, RTC Features ■ 32-bit RX CPU core  32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz  Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations  Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with five-stage pipeline  Variable-length instruction format, ultra-compact code  On-chip debugging circuit ■ Low power consumption functions  Operation from a single 1.8 to 3.
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