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R5F51111ADFL - 32 MHz 32-bit RX MCUs

Download the R5F51111ADFL datasheet PDF. This datasheet also covers the R5F51115AGFM variant, as both devices belong to the same 32 mhz 32-bit rx mcus family and are provided as variant models within a single manufacturer datasheet.

Description

Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit register Ba

Features

  • 32-bit RX CPU core.
  • 32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz.
  • Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations.
  • Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle).
  • Fast interrupt.
  • CISC Harvard architecture with five-stage pipeline.
  • Variable-length instruction format, ultra-compact code.
  • On-chip debuggi.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (R5F51115AGFM_Renesas.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Renesas

Part Number Description
R5F51111ADFL 32 MHz 32-bit RX MCUs
R5F51111ADFK 32 MHz 32-bit RX MCUs
R5F51111ADFK 32 MHz 32-bit RX MCUs
R5F51111ADFM 32 MHz 32-bit RX MCUs
R5F51111ADFM 32 MHz 32-bit RX MCUs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Datasheet RX111 Group Renesas MCUs R01DS0190EJ0100 Rev.1.00 Jun 19, 2013 32 MHz 32-bit RX MCUs, 50 DMIPS, up to 128 Kbytes of flash memory, USB 2.0 full-speed host/function/OTG, up to 6 comms channels, 12-bit A/D, 8-bit D/A, RTC Features ■ 32-bit RX CPU core  32 MHz maximum operating frequency Capable of 50 DMIPS when operating at 32 MHz  Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations  Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with five-stage pipeline  Variable-length instruction format, ultra-compact code  On-chip debugging circuit ■ Low power consumption functions  Operation from a single 1.8 to 3.
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