Datasheet4U Logo Datasheet4U.com

R5F12048GSP - MCU

This page provides the datasheet information for the R5F12048GSP, a member of the R5F12008ANS MCU family.

Features

  • Low power consumption technology.
  • VDD = single power supply voltage of 2.4 to 5.5 V.
  • HALT mode.
  • STOP mode RL78 CPU core.
  • CISC architecture with 3-stage pipeline.
  • Minimum instruction execution time: Can be changed from high speed (0.0625 μs: @ 16 MHz operation with high-speed on-chip oscillator) to low speed (1.0 μs: @ 1 MHz operation).
  • Address space: 1 MB.
  • General-purpose registers: (8-bit register × 8) × 4 banks.
  • On-chip RAM: 1 KB Code flash memory.

📥 Download Datasheet

Datasheet preview – R5F12048GSP

Datasheet Details

Part number R5F12048GSP
Manufacturer Renesas
File Size 2.85 MB
Description MCU
Datasheet download datasheet R5F12048GSP Datasheet
Additional preview pages of the R5F12048GSP datasheet.

📁 Similar Datasheet

  • R5F10xxxxxx - Combines Multi-channel 12-Bit A/D Converter (Renesas Technology)
  • R5F211A1DD - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A1DSP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A1SP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A2DD - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A2DSP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A2NP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A2SP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A3DD - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A3DSP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
DATASHEET RL78/G15 RENESAS MCU R01DS0420EJ0130 Rev.1.30 Aug 9, 2024 True low-power platform, 54-µA/MHz operating current, TA = 125°C operation, from 8 to 20 pins, 4 to 8 KB code flash memory, 1 KB RAM, 2.4 to 5.5 V 1. OUTLINE 1.1 Features Low power consumption technology  VDD = single power supply voltage of 2.4 to 5.5 V  HALT mode  STOP mode RL78 CPU core  CISC architecture with 3-stage pipeline  Minimum instruction execution time: Can be changed from high speed (0.0625 μs: @ 16 MHz operation with high-speed on-chip oscillator) to low speed (1.
Published: |