Datasheet4U Logo Datasheet4U.com

ISL6617 - PWM Doubler

Description

ISENA+ Output of the differential amplifier for Channel A.

the sensed voltage to set the current gain.

Input of the differential amplifier for Channel A.

Features

  • Tri-State input and outputs that recognize a high-impedance state, working together with Intersil multiphase PWM controllers and driver stages to prevent negative transients on the controlled output voltage when operation is suspended. This feature eliminates the need for the schottky diode that may be utilized in a power system to protect the load from excessive negative output voltage damage.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ISL6610 Dual Synchronous Rectified MOSFET Drivers Intersil Corporation
ISL6610A Dual Synchronous Rectified MOSFET Drivers Intersil Corporation
ISL6614A Dual Advanced Synchronous Rectified Buck MOSFET Driver Intersil
ISL60007 High Precision FGA Voltage References Intersil Corporation
ISL6142 Negative Voltage Hot Plug Controller Intersil Corporation

Other Datasheets by Renesas

Part Number Description
ISL6617A PWM Doubler
ISL6611A Phase Doubler
ISL6612 Advanced Synchronous Rectified Buck MOSFET Drivers
ISL6612A Advanced Synchronous Rectified Buck MOSFET Drivers
ISL6612B Advanced Synchronous Rectified Buck MOSFET Drivers

Full PDF Text Transcription

Click to expand full text
DATASHEET ISL6617 PWM Doubler with Phase Shedding Function and Output Monitoring Feature FN7564 Rev 0.00 February 4, 2010 The ISL6617 utilizes Intersil’s proprietary Phase Doubler scheme to modulate two-phase power trains with single PWM input. It doubles the number of phases that Intersil’s multi-phase controllers ISL63xx can support. When the enable pin (EN_PH_SYNC) is pulled low, the PWM input is pulled high. This simplifies the phase shedding implementation for some Intersil controllers (VR10, VR11, VR11.1, and VR12 family) that can disable the respective and higher phase(s) by pulling the respective PWM line high. The ISL6617 is designed to minimize the number of analog signals that interface between the controller and drivers in high phase count scalable applications.
Published: |