IDT2309A Datasheet PDF - Renesas 3.3V ZERO DELAY CLOCK BUFFER Specs

IDT2309A - 3.3V ZERO DELAY CLOCK BUFFER

Datasheet Summary

Description

The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

Features

Phase-Lock Loop Clock Distribution.
10MHz to 133MHz operating frequency.
Distributes one clock input to one bank of five and one bank of four outputs.
Separate output enable for each output bank.
Output Skew < 250ps.
Low jitter.

Datasheet Details

Part number	IDT2309A
Manufacturer	Renesas
File Size	199.03 KB
Description	3.3V ZERO DELAY CLOCK BUFFER
Datasheet	IDT2309A Datasheet
Additional preview pages of the IDT2309A datasheet.

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Full PDF Text Transcription

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IDT2309A 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK BUFFER IDT2309A FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT2309A-1 for Standard Drive • IDT2309A-1H for High Drive • No external RC network required • Operates at 3.3V VDD • Available in SOIC and TSSOP packages DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

Published: Aug 3, 2021 |