ICS95V842 - Clock Driver

Datasheet Summary

Features

Low skew, low jitter PLL clock driver.
Feedback pins for input to output synchronization.
Spread Spectrum tolerant inputs.
With bypass mode mux.
Operating frequency 60 to 220 MHz Switching Characteristics:.
CYCLE - CYCLE jitter:.

Renesas

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Datasheet Details

Part number	ICS95V842
Manufacturer	Renesas
File Size	229.14 KB
Description	Clock Driver
Datasheet	ICS95V842 Datasheet
Additional preview pages of the ICS95V842 datasheet.

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Full PDF Text Transcription

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ICS95V842 DDR Phase Lock Loop Clock Driver (60MHz - 220MHz) Recommended Application: 1:2 DDRI Clock Driver Product Description/Features: • Low skew, low jitter PLL clock driver • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • With bypass mode mux • Operating frequency 60 to 220 MHz Switching Characteristics: • CYCLE - CYCLE jitter: <75ps • OUTPUT - OUTPUT skew: <60ps • Period jitter: ±75ps • Half-Period jitter: ±75ps Pin Configuration VDD2.5 1 DDRT0 2 DDRC0 3 GND 4 CLK_INT 5 CLK_INC 6 AVDD 7 AGND 8 ICS95V842 16 GND 15 DDRC1 14 DDRT1 13 VDD2.

Published: Jun 4, 2020 |