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ICS859S0212I - Differential-to-LVPECL/LVDS Clock Multiplexer

Description

The ICS859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz.

The ICS859S0212I has 2 selectable differential PCLKx, nPCLKx clock inputs.

The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS or CML levels.

Features

  • High speed 2:1 differential multiplexer with a 1:2 fanout buffer.
  • Two differential LVPECL or LVDS output pairs.
  • Two selectable differential PCLKx, nPCLKx input pairs.
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML.
  • Maximum output frequency: 3GHz.
  • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input.
  • Part-to-part skew: 100ps (maximum).
  • Propaga.

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Datasheet Details

Part number ICS859S0212I
Manufacturer Renesas
File Size 1.07 MB
Description Differential-to-LVPECL/LVDS Clock Multiplexer
Datasheet download datasheet ICS859S0212I Datasheet

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Full PDF Text Transcription

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2:2, Differential-to-LVPECL/LVDS Clock Multiplexer ICS859S0212I DATA SHEET General Description The ICS859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock Multiplexer which can operate up to 3GHz. The ICS859S0212I has 2 selectable differential PCLKx, nPCLKx clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.
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