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HD74LS75P - Quadruple Bistable Latches

Download the HD74LS75P datasheet PDF. This datasheet also covers the HD74LS75 variant, as both devices belong to the same quadruple bistable latches family and are provided as variant models within a single manufacturer datasheet.

Features

  • complementary Q and Q outputs from a 4-bit latch. Features.
  • Ordering Information Part Name Package Type Package Code Package (Previous Code) Abbreviation HD74LS75P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74LS75FPEL SOP-16 pin (JEITA) PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity).
  • EL (2,000 pcs/reel) Pin Arrangement 1Q 1 1D 2 2D 3 Enable 3-4 4 VCC 5 3D 6 4D 7 4Q 8 Q Q GD GD Q.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS75-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74LS75P
Manufacturer Renesas
File Size 171.53 KB
Description Quadruple Bistable Latches
Datasheet download datasheet HD74LS75P Datasheet

Full PDF Text Transcription

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HD74LS75 Quadruple Bistable Latches REJ03D0416-0300 Rev.3.00 May 10, 2006 The HD74LS75 is ideally suited for use as temporary storage for binary information between processing units and input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high. This device features complementary Q and Q outputs from a 4-bit latch.
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