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HD74LS259P - 8-bit Address Latch

Download the HD74LS259P datasheet PDF. This datasheet also covers the HD74LS259 variant, as both devices belong to the same 8-bit address latch family and are provided as variant models within a single manufacturer datasheet.

Features

  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74LS259P DILP-16 pin PRDP0016AE-B (DP-16FV).
  • PRSP0016DH-B HD74LS259FPEL SOP-16 pin (JEITA) (FP-16DAV) FP HD74LS259RPEL SOP-16 pin (JEDEC) PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity).
  • EL (2,000 pcs/reel) EL (2,500 pcs/reel) Rev.2.00, Feb.18.2005, page 1 of 7 HD74LS259 P.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS259-Renesas.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
HD74LS259 8-bit Addressable Latches Hitachi Semiconductor
HD74LS251 1 of 8 Data Selectors/Multiplexers Hitachi Semiconductor
HD74LS253 Dual 4-line-to-1-line Data Selectors/Multiplexers Hitachi Semiconductor
HD74LS257 Quadruple 2-line-to-1-line Data Selectors/Multiplexers Hitachi Semiconductor
HD74LS258 Quadruple 2-line-to-1-line Data Selectors/Multiplexers Hitachi Semiconductor

Other Datasheets by Renesas

Part Number Description
HD74LS259 8-bit Address Latch
HD74LS251 1 of 8 Data Selector/Multiplexer
HD74LS251P 1 of 8 Data Selector/Multiplexer
HD74LS253 Dual 4-line-to-1-line Data Selectors/Multiplexers
HD74LS253P Dual 4-line-to-1-line Data Selectors/Multiplexers

Full PDF Text Transcription

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HD74LS259 8-bit Address Latch REJ03D0471–0200 Rev.2.00 Feb.18.2005 This 8-bit addressable latch is designed for general purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. This is multifunctional device capable of storing single-line data in eight addressable latches, and being a 1-to-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch will follow the data input with all unaddressed latches remaining in their previous states.
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