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HD74LS156P - Dual 2-line-to-4-line Decoders/Demultiplexers

Download the HD74LS156P datasheet PDF. This datasheet also covers the HD74LS156 variant, as both devices belong to the same dual 2-line-to-4-line decoders/demultiplexers family and are provided as variant models within a single manufacturer datasheet.

Features

  • dual 1-line-to-4-line demultiprexer with individual strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74LS156-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74LS156P
Manufacturer Renesas
File Size 190.30 KB
Description Dual 2-line-to-4-line Decoders/Demultiplexers
Datasheet download datasheet HD74LS156P Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74LS156 Dual 2-line-to-4-Line Decoders / Demultiplexers Hitachi Semiconductor
HD74LS15 Triple 3-input Positive AND Gates Hitachi Semiconductor
HD74LS151 1-of-8 Data Selectors/Multiplexers Hitachi Semiconductor
HD74LS152 1-of-8 Data Selectors/Multiplexers Hitachi Semiconductor
HD74LS153 Dual 4-Line to 1-Line Data Selectors/Multiplexers Hitachi Semiconductor

Other Datasheets by Renesas

Part Number Description
HD74LS156 Dual 2-line-to-4-line Decoders/Demultiplexers
HD74LS15 Triple 3-input Positive AND Gates
HD74LS151 1-of-8 Data Selector/Multiplexer
HD74LS151P 1-of-8 Data Selector/Multiplexer
HD74LS152 1-of-8 Data Selector / Multiplexer

Full PDF Text Transcription

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HD74LS156 Dual 2-line-to-4-line Decoders / Demultiplexers (with open collector outputs) REJ03D0441–0300 Rev.3.00 Jul.13.2005 This circuit features dual 1-line-to-4-line demultiprexer with individual strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating.
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