8SLVP1212 Datasheet PDF - Renesas LVPECL Output Fanout Buffer Specs

8SLVP1212 - LVPECL Output Fanout Buffer

Datasheet Summary

Description

The 8SLVP1212 is a high-performance, 12 output differential LVPECL fanout buffer.

The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

The 8SLVP1212 is characterized to operate from a 3.3V and 2.5V power supply.

Features

Twelve low skew, low additive jitter LVPECL outputs.
Two selectable, differential clock inputs.
Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML.
Maximum input clock frequency: 2GHz.
LVCMOS interface levels for the control input (input select).
Output skew: 33ps (maximum).
Propagation delay: 550ps (maximum).
Low additive phase jitter, RMS at fREF = 156.25MHz, VPP = 1V, 12kHz.
2.

Datasheet Details

Part number	8SLVP1212
Manufacturer	Renesas
File Size	1.01 MB
Description	LVPECL Output Fanout Buffer
Datasheet	8SLVP1212 Datasheet
Additional preview pages of the 8SLVP1212 datasheet.

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Full PDF Text Transcription

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Low Phase Noise, 1-to-12, 3.3V, 2.5V LVPECL Output Fanout Buffer 8SLVP1212 DATASHEET Description The 8SLVP1212 is a high-performance, 12 output differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1212 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs.

Published: Sep 26, 2023 |