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8P34S1102 - 1:2 LVDS 1.8V / 2.5V Fanout Buffer

Description

The 8P34S1102 is a high-performance differential LVDS fanout buffer.

The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals.

Features

  • Two low skew, low additive jitter LVDS output pairs.
  • One differential clock input pair.
  • Differential CLK, nCLK pairs can accept the following differential input levels: LVDS, CML.
  • Maximum input clock frequency: 51.2GHz.
  • Output skew: 3ps (typical).
  • Propagation delay: 400ps (maximum).
  • Low additive phase jitter, RMS; fREF = 156.25MHz, 10kHz.
  • 20MHz: 34fs (typical).
  • Device current consumption (IDD):.
  • 40mA typical: 1.8V.
  • 50mA typical: 2.

📥 Download Datasheet

Datasheet preview – 8P34S1102

Datasheet Details

Part number 8P34S1102
Manufacturer Renesas
File Size 1.34 MB
Description 1:2 LVDS 1.8V / 2.5V Fanout Buffer
Datasheet download datasheet 8P34S1102 Datasheet
Additional preview pages of the 8P34S1102 datasheet.

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Full PDF Text Transcription

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1:2 LVDS 1.8V / 2.5V Fanout Buffer for 1PPS and High-Speed Clocks 8P34S1102 Datasheet Description The 8P34S1102 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of 1PPS signals or high-frequency, very low additive phase-noise clock and data signals. The 8P34S1102 supports fail-safe operation and is characterized to operate from a 1.8V or 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8P34S1102 ideal for those clock distribution applications demanding well-defined performance and repeatability. One differential input and two low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the differential device input.
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