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843S06 - PLL Clock Synthesizer

Datasheet Summary

Description

The 843S06 is a low voltage, low skew 3.3V LVPECL Clock Synthesizer.

The device targets clock distribution in SDH/SONET telecommunication systems but is well suited for a wide range of applications requiring high performance high-speed clock synthesis.

Features

  • Six differential 3.3V LVPECL outputs 1,244.16/622.08MHz; 1,244.16/622.08MHz 622.08/311.04MHz; 311.04/155.52MHz 155.52/77.76MHz; 77.76/38.88MHz.
  • Three selectable differential reference clock inputs Clock frequency range: 19MHz to 622MHz.
  • REF_CLKx, nREF_CLKx pairs can accept the following differential input level: LVPECL.
  • Intrinsic jitter: 0.017mUI @ 622MHz RMS.
  • Output skew: 200ps (maximum).
  • Optional external VCXO possible.

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Datasheet Details

Part number 843S06
Manufacturer Renesas
File Size 474.30 KB
Description PLL Clock Synthesizer
Datasheet download datasheet 843S06 Datasheet
Additional preview pages of the 843S06 datasheet.

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Full PDF Text Transcription

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Low Voltage, Low Skew, 1.244GHz PLL Clock Synthesizer 843S06 DATA SHEET GENERAL DESCRIPTION The 843S06 is a low voltage, low skew 3.3V LVPECL Clock Synthesizer. The device targets clock distribution in SDH/SONET telecommunication systems but is well suited for a wide range of applications requiring high performance high-speed clock synthesis. The device implements a fully integrated multiplying PLL including: • An on-chip analog voltage controlled oscillator (VCO) • Phase-frequency detector • Programmable frequency dividers (prescalers) The loop filter is external in order to optimize the PLL for different applications. As an option, the 843S06 may be operated with an external voltage controlled crystal oscillator for applications demanding a high-Q oscillator.
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