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650R-07ILF - NETWORKING CLOCK SOURCE

This page provides the datasheet information for the 650R-07ILF, a member of the 650R-07LF NETWORKING CLOCK SOURCE family.

Datasheet Summary

Description

The ICS650-07C is a low cost, low jitter, high performance clock synthesizer for networking applications.

Features

  • Packaged in 20-pin tiny SSOP (QSOP).
  • Pb (lead) free package.
  • 12.5 MHz or 25.00 MHz fundamental crystal or clock input.
  • Six output clocks with selectable frequencies.
  • SDRAM frequencies of 67, 83, 100, and 133 MHz.
  • Buffered crystal reference output.
  • Zero ppm synthesis error in all clocks.
  • Ideal for PMC-Sierra’s ATM switch chips.
  • Full CMOS output swing with 25 mA output drive capability at TTL levels.
  • Advance.

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Datasheet preview – 650R-07ILF

Datasheet Details

Part number 650R-07ILF
Manufacturer Renesas
File Size 354.41 KB
Description NETWORKING CLOCK SOURCE
Datasheet download datasheet 650R-07ILF Datasheet
Additional preview pages of the 650R-07ILF datasheet.

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Full PDF Text Transcription

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NETWORKING CLOCK SOURCE DATASHEET ICS650-07C Description The ICS650-07C is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25.00 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. The ICS650-07C outputs all have 0 ppm synthesis error. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks. Block Diagram Features • Packaged in 20-pin tiny SSOP (QSOP) • Pb (lead) free package • 12.5 MHz or 25.
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