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V360EPC - Local Bus to PCI Bridge

Description

Table 2 below lists the pin types found on the V360EPC.

Table 3 describes the function of each pin on the V360EPC.

Table 5 lists the pins by pin number.

Features

  • like Hot Swap and DMA chaining. The PCI bus can be run at full 33MHz, independent of local bus clock rate. The overall throughput of the system is dramatically improved by increasing the FIFO m o . c U 4 t e e h S a t a m . D o . c w U 4 t w e e w h aS.
  • Hot swapping capability.
  • 16 8-bit bi-directional mailbox registers with doorbell interrupts.
  • Flexible PCI and local interrupt management.
  • 33MHz and 50MHz local bus versions.
  • Optional power-on serial EEPR.

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Datasheet Details

Part number V360EPC
Manufacturer QuickLogic
File Size 277.63 KB
Description Local Bus to PCI Bridge
Datasheet download datasheet V360EPC Datasheet

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Full PDF Text Transcription

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• Glueless interface to i960Cx/Hx and AMD29030/40 processors • Configurable for primary master, bus master or target operation. • Type 0 and type 1 configuration cycles. • Up to 1Kbyte burst access on PCI or local. • Large, 640-byte FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION™ architecture • 64-byte read FIFO per aperture. • Enhanced support for 8/16-bit local bus devices with programmable region sizes. • 3.3 volt support • Dual bi-directional address space remapping • Fully compliant with PCI 2.1 specification V360EPC provides the highest performance, most flexible, and most economical method to directly connect i960Cx/Hx or AMD2930/40 processors to the PCI bus.
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