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V7001 - SDR-SDRAM Memory Controller

Description

Document Self checking Verification Suite Synthesis Scripts

QualCore Logic, Inc.

Features

  • JEDEC standard SDR-SDRAM supported.
  • Transaction pipeline for maximum utilization of the Memory Bus.
  • 3 Request buffers for transaction pipeline.
  • Supports CAS latencies of 1, 2 and 3.
  • 4 or 8 beat burst transactions supported.
  • Supports up to 4 chip selects of Memory devices.
  • Page mode support for up to 16 open pages.
  • Supports flexible Row and Column addressing.
  • Supports up to 4GB of Memory Address space.
  • Supp.

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Datasheet Details

Part number V7001
Manufacturer Qualcore
File Size 67.03 KB
Description SDR-SDRAM Memory Controller
Datasheet download datasheet V7001 Datasheet

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