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QP27C256L - 256 Kilobit (32K x 8) CMOS EPROM

Download the QP27C256L datasheet PDF. This datasheet also covers the QP27C256 variant, as both devices belong to the same 256 kilobit (32k x 8) cmos eprom family and are provided as variant models within a single manufacturer datasheet.

Description

The QP27C256 is a 32Kx8 (256-Kbit), UV erasable programmable read-only memory.

Features

  • fast single address location programming. The QP27C256 meets the same specification requirements and utilizes the same programming methodology as the AMD 27C256 that it replaces. Products are available in windowed and non-windowed (OTP) ceramic hermetic packages. Data is typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable ( OE ) and Chip Enable ( CE ) pins, eliminating bus contention in a mu.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (QP27C256-QPSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number QP27C256L
Manufacturer QP Semiconductor
File Size 169.10 KB
Description 256 Kilobit (32K x 8) CMOS EPROM
Datasheet download datasheet QP27C256L Datasheet

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Other Datasheets by QP Semiconductor

Part Number Description
QP27C256 256 Kilobit (32K x 8) CMOS EPROM
QP27C128 128 Kilobit (16K x 8) CMOS EPROM
QP26LS31 Quad High Speed Differential Line Driver
QP26LS32 Quad Differential Line Receiver
QP26LS33 Quad Differential Line Receiver

Full PDF Text Transcription

Click to expand full text
QP27C256 & QP27C256L QP27C256 – 256 Kilobit (32K x 8) CMOS EPROM June 18, 2009 General Description The QP27C256 is a 32Kx8 (256-Kbit), UV erasable programmable read-only memory. It operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The QP27C256 meets the same specification requirements and utilizes the same programming methodology as the AMD 27C256 that it replaces. Products are available in windowed and non-windowed (OTP) ceramic hermetic packages. Data is typically accessed in less than 55 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable ( OE ) and Chip Enable ( CE ) pins, eliminating bus contention in a multiple bus system.
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