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High-Performance Surface-Mount TTL Delay Lines
n Five equal taps in 20% increments of total delay. n Lumped constant, active series. www.DataSheet4U.com n Transfer-molded packaging for highest reliability. n Designed for leading edge timing. Trailing edge
CTTLDL, BJTTLDL, GBTTLDL, BTTLDL
n Military models with temperature range -55 to
timing available.
n Supports Schottky TTL, FAST, and FACT logics. n Fanout 1 -- 20 loads; logic 0 -- 10 loads. n Temperature coefficient +2 ns or +4% (whichever is
greater) at maximum delay, 0 to 70oC.
+125oC and ceramic package IC to meet MIL-STD883C, but not screened to that specification, add suffix “M” to part number. n Military models as above, but with ceramic package IC screened to MIL-STD 883C and 38510, add suffix “MX” to part number.
BJTTLDL Datasheet
