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PG 320240-D
OUTLINE DIMENSION & BLOCK DIAGRAM
74.04 4.44 4.02 6.63 H1 H2 9.53
7.11
148.02 0.5 136.2 120.14(V/A) 115.17(A/A)
(8.0)
190 10.0 CCFL
59.81
0.33 0.03 (P2.54 x 2) 5.08 Molex 50-57-9403 86.0
20 19 1
120.24 0.5 112.2 105.4 92.14(V/A) 86.37(A/A)
320 x 240 Dots
0.03 0.33
1.6
HLOE4- 3.5
HOLE20- 1.0 PAD20- 1.4 139.98
(P2.54 x 9) 22.86
21.06
2.54 5.0
2
4.02
/WR /RD Ao /CS /RES DB0~DB7 Vss Vdd (TEST POINT) Vee VLCD A K
9
4 3 3
CONTROLLER SED 1335
15 8
COM COM COM 32K RAM CRYSTAL
80 80 80 80 80 80 80
LCD PANEL
8
COL
9 8
COL
8
COL
8
COL
8
2
NEGATIVE VOLTAGE / TEMP. COMPENSATION
BIAS
TO COM, COL, LSI
BACKLIGHT
The tolerance unless classified
Overall Size View Area Dot Size Dot Pitch 148.02 x 120.24 120.14 x 92.14 0.33 x 0.33 0.36 x 0.36
0.
PG320240-D Datasheet
