74HC112
FEATURES
- Asynchronous set and reset
- Output capability: standard
- ICC category: flip-flops GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74HC/HCT112 are dual negative-edge triggered JK-type flip-flops featuring individual n J, n K, clock (n CP), set (n SD) and reset (n RD) inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT112
The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the levels at the other inputs. A HIGH level at the clock (n CP) input enables the n J and n K inputs and data will be accepted. The n J and n K inputs control the state changes of the flip-flops as shown in the function table. The n J and n K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Output state changes are initiated by the...
