PI6C5930 Datasheet PDF - Pericom Semiconductor Low Skew CMOS PLL Clock Driver Specs

PI6C5930 - Low Skew CMOS PLL Clock Driver

Datasheet Summary

Description

The PI6C5930 clock driver uses a PLL (phase-locked loop) to reduce time skew between a reference clock input (SYNC) and the outputs.

An internal loop filter eliminates the need for external compensation.

Features

Wide frequency range: 100 MHz max.
Five Q and one Q/2 outputs.
Output skew < 250ps (rising edges).
Internal RC loop filter network.
Low noise TTL-compatible outputs.
Balanced drive outputs: +24mA.
Outputs Hi-Z and registers reset when OE = LOW.
PLL bypass for testing and low-frequency.

Datasheet Details

Part number	PI6C5930
Manufacturer	Pericom Semiconductor
File Size	216.77 KB
Description	Low Skew CMOS PLL Clock Driver
Datasheet	PI6C5930 Datasheet
Additional preview pages of the PI6C5930 datasheet.

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Published: Apr 2, 2010 |