PDM41024
Features n
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Description
The PDM41024 is a high-performance CMOS static RAM organized as 131,072 x 8 bits. Writing is acplished when the write enable (WE) and the chip enable (CE1) inputs are both LOW and CE2 is HIGH. Reading is acplished when WE and CE2 remain HIGH and CE1 and OE are both LOW. The PDM41024 operates from a single +5V power supply and all the inputs and outputs are fully TTLpatible. The PDM41024 es in two versions: the standard power version (SA) and the low power version (LA). The two versions are functionally the same and differ only in their power consumption. The PDM41024 is available in a 32-pin plastic TSOP (I), and a 300-mil and 400-mil plastic SOJ.
High-speed access times ’l: 10, 12 and 15 ns Ind’l: 12 and 15 ns Low power operation (typical)
- PDM41024SA Active: 450 m W Standby: 50 m W
- PDM41024LA Active: 400 m W Standby: 25m W Single +5V (±10%) power supply TTL-patible inputs and outputs Packages Plastic SOJ (300 mil)
- TSO Plastic SOJ (400 mil)
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