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PM5392 - SATURN User Network Interface

Download the PM5392 datasheet PDF. This datasheet also covers the PM5392_PMC variant, as both devices belong to the same saturn user network interface family and are provided as variant models within a single manufacturer datasheet.

Description

The S/UNI-9953-POS is a single chip ATM, POS User-Network Interface operating at 9953.28 Mbit/s.

The S/UNI 9953-POS is intended for use in OC192c and high-density OC-48c POS/ATM applications.

Provides ATM and POS payload processing for: STS-192c (STM-64-64c) 4

Features

  • Supports framing, scrambling/ descrambling and pointer processing for the following:.
  • STS-192c (STM-64-64c).
  • 4 x STS-48c (4 x STM-16-16c).
  • STS-192 (STM-64) channelized down to STS-48c (STM-16c).
  • Supports alarm signal insertion/detection, B1/2/3 processing and insertion/termination of SONET Section/Line/Path overhead bytes (or SDH equivalents). POS/ATM.
  • Implements the ATM Forum User Network Interface Specification and the ATM physical lay.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PM5392_PMC-Sierra.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PM5392
Manufacturer PMC-Sierra
File Size 41.07 KB
Description SATURN User Network Interface
Datasheet download datasheet PM5392 Datasheet

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Full PDF Text Transcription

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Advance PM5392 S/UNI®-9953-POS SATURN® User Network Interface for 9.953 Gbit/s GENERAL DESCRIPTION • The S/UNI-9953-POS is a single chip ATM, POS User-Network Interface operating at 9953.28 Mbit/s. The S/UNI 9953-POS is intended for use in OC192c and high-density OC-48c POS/ATM applications. • Provides ATM and POS payload processing for: • STS-192c (STM-64-64c) • 4 x STS-48c (4 x STM-16-16c). • STS-192 (STM-64) channelized down to STS-48c (STM-16c). • Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615(1619)/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF). GENERAL • Provides internal FIFOs (16 KB ingress, 20 KB egress) to accommodate system latencies.
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