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NLV74VHC1G50 - Buffer

Datasheet Summary

Features

  • Designed for 2.0 V to 5.5 V VCC Operation.
  • 3.5 ns tPD at 5 V (typ).
  • Inputs/Outputs Over.
  • Voltage Tolerant up to 5.5 V.
  • IOFF Supports Partial Power Down Protection.
  • Source/Sink 8 mA at 3.0 V.
  • Available in SC.
  • 88A, TSOP.
  • 5, SOT.
  • 953 and UDFN6 Packages.
  • Chip Complexity < 100 FETs.
  • NLV Prefix for Automotive and Other.

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Buffer NLV74VHC1G50, NLV74VHC1GT50 The NLV74VHC1G50 / NLV74VHC1GT50 is an advanced high speed CMOS buffer in tiny footprint packages. The NLV74VHC1G50 has CMOS level input thresholds while the NLV74VHC1GT50 has TTL level input thresholds. The input structures provide protection when voltages up to 5.5 V are applied, regardless of the supply voltage. This allows the device to be used to interface 5 V circuits to 3 V circuits. Some output structures also provide protection when VCC = 0 V and when the output voltage exceeds VCC. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. Features • Designed for 2.0 V to 5.5 V VCC Operation • 3.
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