fanout buffer designed with clock distribution in mind.
Key Features
two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part.
to.
part skew down to an output.
to.
output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task. To ensu.
Full PDF Text Transcription for MC100LVE210 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
MC100LVE210. For precise diagrams, and layout, please refer to the original PDF.
MC100LVE210 3.3V ECL Dual 1:4, 1:5 Differential Fanout Buffer Description The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clo...
View more extracted text
oltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part−to−part skew down to an output−to−output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task.