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SCAN18373T - Transparent Latch

Description

The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals.

Features

  • n n n n n n n n n n IEEE 1149.1 (JTAG) Compliant Buffered active-low latch enable TRI-STATE outputs for bus-oriented.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SCAN18373T Transparent Latch with TRI-STATE Outputs September 1998 SCAN18373T Transparent Latch with TRI-STATE ® Outputs General Description The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). Features n n n n n n n n n n IEEE 1149.
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