DM54122
Description
The ’122 features positive and negative DC level triggering inputs plementary outputs an optional 10 k X internal timing resistor and an overriding Direct Clear (CD) input When the circuit is in the quasi-stable (delay) state another trigger applied to the inputs (per Truth Table) will cause the delay period to start again without disturbing the outputs This process can be repeated indefinitely and thus the output pulse period (Q HIGH Q LOW) can be made as long as desired Alternatively a delay period can be terminated by a LOW signal applied to CD which also prevents triggering An internal connection from CD to the input gate makes it possible to trigger the circuit by a positive-going signal on CD as shown in the Truth Table For timing capacitor values greater than 1000 p F the output pulse width is defined as follows tw e 0 32 RXCX (1 0 a 0 7 RX) Where tw is in ns RX is in k X and CX is in p F
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 10212
- 2 TL F 10212
-...
