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CR16MUS5 - Family of CompactRISC 16-Bit Microcontrollers

Download the CR16MUS5 datasheet PDF. This datasheet also covers the CR1 variant, as both devices belong to the same family of compactrisc 16-bit microcontrollers family and are provided as variant models within a single manufacturer datasheet.

Description

The family of CompactRISC 16-bit microcontrollers offer the high performance of a RISC architecture while retaining the advantages of a traditional Complex Instruction Set Computer (CISC): compact code, on-chip memory and I/O, and reduced cost.

Features

  • and low power consumption, resulting in decreased system cost. Block Diagram Fast Osc Slow Osc CR16B Core Processing Unit Clock Generator Power-on-Reset Core Bus Peripheral Bus Controller 48k Flash Program Memory 2 kbyte RAM 640 Bytes EEPROM Data Memory boot ROM Interrupt Power-Save Control Management (ICU).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CR1-6ME.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
CR16MUS9 Family of CompactRISC 16-Bit Microcontrollers
CR16M9S5 Family of CompactRISC 16-Bit Microcontrollers
CR16MAR5 Family of 16-bit CAN-enabled CompactRISC Microcontrollers
CR16MAS5 Family of 16-bit CAN-enabled CompactRISC Microcontrollers
CR16MAS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers

Full PDF Text Transcription

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CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/ CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/ CR16M9S5/CR16MUS5/ CR16MUS9/ Family of CompactRISC 16-Bit Microcontrollers December 2001 CR16MES5/CR16MES9/CR16MFS5/CR16MFS9/ CR16MHS5/CR16MHS9/CR16MNS5/CR16MNS9/ CR16M9S5/CR16MUS5/CR16MUS9/ Family of CompactRISC 16-Bit Microcontrollers 1.0 General Description The family of CompactRISC 16-bit microcontrollers offer the high performance of a RISC architecture while retaining the advantages of a traditional Complex Instruction Set Computer (CISC): compact code, on-chip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 20 million instructions per second (MIPS) at a clock rate of 20 MHz.
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