74LS352
Description
Each of these data selectors multiplexers contains inverters and drivers to supply fully plementary on-chip binary decoding data selection to the AND-OR-invert gates Separate strobe inputs are provided for each of the two four-line sections
Features
Inverting version of DM54 74LS153 Permits multiplexing from N lines to 1 line
Performs parallel-to-serial conversion Strobe (enable) line provided for cascading (N lines to n lines) High fan-out low-impedance totem-pole outputs Typical average propagation delay times From data 15 ns From strobe 19 ns From select 22 ns Typical power dissipation 31 m W
Connection Diagram
Dual-In-Line Package
Function Table
Select Inputs B X L L L L H H H H A X L L H H L L H H C0 X L H X X X X X X Data Inputs C1 X X X L H X X X X C2 X X X X X L H X X C3 X X X X X X X L H Strobe G H L L L L L L L L Output Y H H L H L H L H L
Select inputs A and B are mon to both sections H e High Level L e Low Level X e Don’t Care
TL F 6425
-...
