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SAA7201 - Integrated MPEG2 AVG decoder

General Description

The SAA7201 is an MPEG2 decoder which combines audio decoding and video decoding.

Additionally to these basic MPEG functions it also provides means for enhanced graphics and/or on-screen display.

Key Features

  • General.
  • Uses single external Synchronous DRAM (SDRAM) organized as 1M × 16 interfacing at 81 MHz; compatible with the SDRAM ‘lite’ or ‘PC’.
  • Fast external CPU interface; 16-bit data + 8-bit address.
  • Dedicated input for audio and video data in PES or ES format; data input rate: ≤9 Mbytes/s in byte mode; ≤20 Mbit/s in bit serial mode; audio and/or video data can also serve as input via CPU interface.
  • Single 27 MHz external clock for time base reference and inter.

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Full PDF Text Transcription for SAA7201 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for SAA7201. For precise diagrams, and layout, please refer to the original PDF.

INTEGRATED CIRCUITS DATA SHEET SAA7201 Integrated MPEG2 AVG decoder Objective specification File under Integrated Circuits, IC02 1997 Jan 29 Philips Semiconductors Objecti...

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r Integrated Circuits, IC02 1997 Jan 29 Philips Semiconductors Objective specification Integrated MPEG2 AVG decoder FEATURES General • Uses single external Synchronous DRAM (SDRAM) organized as 1M × 16 interfacing at 81 MHz; compatible with the SDRAM ‘lite’ or ‘PC’ • Fast external CPU interface; 16-bit data + 8-bit address • Dedicated input for audio and video data in PES or ES format; data input rate: ≤9 Mbytes/s in byte mode; ≤20 Mbit/s in bit serial mode; audio and/or video data can also serve as input via CPU interface • Single 27 MHz external clock for time base reference and internal processing; all required decoding

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