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SAA7157 - Clock signal generator circuit for digital TV systems SCGC

Description

The SAA7157 generates all clock signals required for a digital TV system suitable for the SAA715x family and the SAA7199B (DENC).

The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator mode (VCO).

Features

  • Clock generation suitable for digital TV systems (line-locked).
  • PLL frequency multiplier to generate 4 times of input frequency SAA7157.
  • Dividers to generate clocks LL1.5A, LL1.5B, LL3A and LL3B (4th and 2nd multiples of input frequency).
  • PLL mode or VCO mode selectable.
  • Reset control and power fail detection.
  • Suitable for.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET SAA7157 Clock signal generator circuit for digital TV systems (SCGC) Product specification File under Integrated Circuits, IC02 May 1992 Philips Semiconductors Product specification Clock signal generator circuit for digital TV systems (SCGC) FEATURES • Clock generation suitable for digital TV systems (line-locked) • PLL frequency multiplier to generate 4 times of input frequency SAA7157 • Dividers to generate clocks LL1.5A, LL1.
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