P60D145_SDS Datasheet PDF - NXP dual interface secure microcontroller Specs

P60D145_SDS - dual interface secure microcontroller

Datasheet Summary

Description

The P60D145 dual interface secure microcontroller is part of the most recent P60Step-Up!

family generation and builds on the IntegralSecurity architecture.

Features

2.1 Key features.
User EEPROM: up to 142,5 KB.
User ROM:.
512 KB, y = P or M or D or J.
586 KB, y = X.
User RAM: up to 10176 Bytes.
Dual Interface Type according to ISO/IEC 14443/7816.
Rich option choice of certified convergence implementations:.
y = P (Plain, no convergence implementations).
y = X (Plain, no convergence implementations, extended User ROM).
y = M (MIFARE Plus/Classic implementation).

Datasheet Details

Part number	P60D145_SDS
Manufacturer	NXP
File Size	500.30 KB
Description	dual interface secure microcontroller
Datasheet	P60D145_SDS Datasheet
Additional preview pages of the P60D145_SDS datasheet.

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Full PDF Text Transcription

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P60D145_SDS SmartMX2 Family P60D145y Rev. 3.0 — 27 September 2016 Public product data sheet COMPANY PUBLIC 1 General description The P60D145 dual interface secure microcontroller is part of the most recent P60Step-Up! family generation and builds on the IntegralSecurity architecture. It delivers unprecedented security, extended memory footprint, and highest performance across all typical up-to-date requested fast transaction cases in Payment and eGov. Furthermore, it comes with comprehensive options of ready-to-use MIFARE™ functionality and certified crypto library modules and can be ordered in various advanced package options for contact, dual interface, and contactless operation. 2 Features and benefits 2.

Published: Oct 11, 2021 |