Download the MIMX9332DVUXMAA datasheet PDF.
This datasheet also covers the MIMX9352DVUXMAA variant, as both devices belong to the same consumer application processors family and are provided as variant models within a single manufacturer datasheet.
Key Features
(Sheet 1 of 3)
Features
Two Cortex®-A55 processors operating up to 1.7 GHz.
32 KB L1 Instruction Cache.
32 KB L1 Data Cache.
64 KB per-core L2 cache.
Media Processing Engine (MPE) with Arm® NeonTM technology supporting the
Advanced Single Instruction Multiple Data architecture.
Floating Point Unit (FPU) with support of the Arm® VFPv4-D16 architecture
Support of 64-bit Arm® v8.2-A architecture
256 KB cluster L3 cache
Parity/ECC protection on L1 cache,.
Full PDF Text Transcription for MIMX9332DVUXMAA (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
MIMX9332DVUXMAA. For precise diagrams, and layout, please refer to the original PDF.
NXP Semiconductors Data Sheet: Technical Data Document Number: IMX93CEC Rev. 1, 04/2023 i.MX 93 Consumer Application Processors Data Sheet A0 Pre-Production Prototype MIM...
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umer Application Processors Data Sheet A0 Pre-Production Prototype MIMX9352DVUXMAA MIMX9332DVUXMAA MIMX9302DVUXDAA MIMX9322DVWXMAA MIMX9312DVWXMAA MIMX9351DVUXMAA MIMX9331DVUXMAA MIMX9301DVUXDAA MIMX9321DVWXMAA MIMX9311DVWXMAA Package Information Plastic Package FCBGA 11 x 11 mm, 0.5 mm pitch FCBGA 9 x 9 mm, 0.5 mm pitch Ordering Information 1 i.MX 93 introduction See Table 2 on page 5 The i.MX 93 family represents NXP’s latest 1. i.MX 93 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 power-optimized processors for smart home, building control, contactless HMI, IoT edge, and Industrial application
MIMX9332DVUXMAA Datasheet
