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HEF4029B - Synchronous up/down counter/ binary/decade counter

Description

The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parall

Features

  • up/down control can be changed at any count; the only restriction on changing the up/down control is that the clock input to the first.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4029B MSI Synchronous up/down counter, binary/decade counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Synchronous up/down counter, binary/decade counter DESCRIPTION The HEF4029B is a synchronous edge-triggered up/down 4-bit binary/BCD decade counter with a clock input (CP), an active LOW count enable input (CE), an up/down control input (UP/DN), a binary/decade control input (BIN/DEC), an overriding asynchronous active HIGH parallel load input (PL), four parallel data inputs (P0 to P3), four parallel
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