BST120
DESCRIPTION
P-channel vertical D-MOS transistor in SOT89 envelope and intended for use in relay, high-speed and line-transformer drivers, using SMD technology. FEATURES
- Very low RDS(on)
- Direct interface to C-MOS
- High-speed switching
- No second breakdown QUICK REFERENCE DATA Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source ON-resistance
- ID = 200 m A;
- VGS = 10 V Transfer admittance
- ID = 200 m A;
- VDS = 15 V PINNING
- SOT89 1 = source 2 = drain 3 = gate Yfs typ. RDS(on)
- VDS ±VGSO
- ID Ptot
BST120 max. max. max. max. typ. max.
60 V 20 V 0,3 A 1 W 4,5 Ω 6 Ω
200 m S
PIN CONFIGURATION handbook, halfpage d g 1 Bottom view 2 3
MAM354 s marking: LM
Fig.1 Simplified outline and symbol.
April 1995
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source...
