BS170
DESCRIPTION
N-channel enhancement mode vertical D-MOS transistor in TO-92 variant envelope and intended for use in relay, high-speed and line-transformer drivers. FEATURES
- Very low RDS(on).
- Direct interface to C-MOS, TTL, etc.
- High-speed switching.
- No secondary breakdown. PINNING
- TO-92 VARIANT 1 = source 2 = gate 3 = drain PIN CONFIGURATION QUICK REFERENCE DATA Drain-source voltage Gate-source voltage Drain current (DC) Total power dissipation up to Tamb = 25 °C Junction temperature Drain-source ON-resistance VGS = 10 V; ID = 200 m A RDS(on) max. VDS VGS ID Ptot Tj max. max. max. max. max.
60 V 15 V 500 m A 830 m W 150 °C 5 Ω handbook, halfpage d
1 2 3 g
MAM146 s
Note: Various pin configurations available.
Fig.1 Simplified outline and symbol.
April 1995
Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Drain-gate voltage...
