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74AUP2T1326 - Low-power Dual Supply Buffer/line Driver

General Description

The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual buffer/line driver with output enable circuitry.

The 74AUP2T1326 is designed for logic-level translation and combines the functions of the 74AUP1G32 and 74AUP2G126.

Key Features

  • I Wide supply voltage range: N VCC(A): 1.1 V to 3.6 V; VCC(B): 1.1 V to 3.6 V. I High noise immunity I Complies with JEDEC standards: N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 2A exceeds 2000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II www. DataSheet4U. com NXP Semiconductors.

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Other Datasheets by NXP Semiconductors

Part Number Description
74AUP2G07 Low-power dual buffer
74AUP2G125 Low-power dual buffer/line driver
74AUP2G17 Low-power dual Schmitt trigger
74AUP2G79 Low-power dual D-type flip-flop
74AUP1G00 Low-power 2-input NAND gate
74AUP1G04 Low-power inverter
74AUP1G06 Low-power inverter
74AUP1G07 Low-power buffer
74AUP1G08 Low-power 2-input AND gate
74AUP1G125 Low-power buffer/line driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AUP2T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 — 1 July 2009 Product data sheet 1. General description The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual buffer/line driver with output enable circuitry. The 74AUP2T1326 is designed for logic-level translation and combines the functions of the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output enable inputs.