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S7L6436U2M - 2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM w/ ODT

Description

The S7L6436U2M and S7L6418U2M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.

They are organized as 2.097,152 words by 36bits for S7L6436U2M and 4,194,304 words by 18 bits for S7L6418U2M.

Features

  • Key Parameters.
  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future fre- quency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
  • Pipelined, double-data rate operation.
  • Common data input/output bus.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Read latency : 2.5 clo.

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Datasheet Details

Part number S7L6436U2M
Manufacturer NETSOL
File Size 409.99 KB
Description 2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM w/ ODT
Datasheet download datasheet S7L6436U2M Datasheet

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S7L1636U2M 512Kx36 & 1Mx18 DDRII+ CIO BL2 SRAM w/ ODT
S7L3218U2M 1Mx36 & 2Mx18 DDRII+ CIO BL2 SRAM w/ ODT
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Full PDF Text Transcription

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SSSS7777LLLL6666444413318668UUUU2222MMMM Preliminary 22MMxx3366 && 44MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM ww// OODDTT 72Mb DDRII+ CIO BL2 w/ ODT SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of NETSOL.
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