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SN54LS197 - 4-STAGE PRESETTABLE RIPPLE COUNTERS

Download the SN54LS197 datasheet PDF. This datasheet also covers the SN54LS197J variant, as both devices belong to the same 4-stage presettable ripple counters family and are provided as variant models within a single manufacturer datasheet.

Description

The LS196 and LS197 are asynchronously presettable decade and binary ripple counters.

The LS196 Decade Counter is partitioned into divide-by-two and divide-by-five sections while the LS197 is partitioned into divide-by-two and divideby-eight sections, with all sections having a separate Clock input.

Features

  • D Suffix 14-Pin Plastic SO-14 -A- 14 8 -B- P 0.25 (0.010) M BM 1 7 PL 7 G C R X 45° D14 PL 0.25 (0.010) M T B S AS.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (SN54LS197J_MotorolaInc.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
SN54LS197 Presettable Decade Or Binary Counters/Latches Texas Instruments
SN54LS197 Presettable Decade Or Binary Counters/Latches Texas Instruments
SN54LS190 PRESETTABLE BCD/DECADE UP/DOWN COUNTER Motorola Inc
SN54LS190 SYNCHRONOUS UP/DOWN COUNTERS Texas Instruments
SN54LS191 SYNCHRONOUS UP/DOWN COUNTERS Texas Instruments

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
SN54LS191 PRESETTABLE BCD/DECADE UP/DOWN COUNTER
SN54LS193 PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
SN54LS136 QUAD 2-INPUT EXCLUSIVE OR GATE
SN54LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER
SN54LS148 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

Full PDF Text Transcription

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4-STAGE PRESETTABLE RIPPLE COUNTERS The SN54/74LS196 decade counter is partitioned into divide-by-two and divide-by-five sections which can be combined to count either in BCD (8, 4, 2, 1) sequence or in a bi-quinary mode producing a 50% duty cycle output. The SN54/74LS197 contains divide-by-two and divide-by-eight sections which can be combined to form a modulo-16 binary counter. Low Power Schottky technology is used to achieve typical count rates of 70 MHz and power dissipation of only 80 mW. Both circuit types have a Master Reset (MR) input which overrides all other inputs and asynchronously forces all outputs LOW. A Parallel Load input (PL) overrides clocked operations and asynchronously loads the data on the Parallel Data inputs (Pn) into the flip-flops.
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