Full PDF Text Transcription for MC74F112 (Reference)
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MC74F112. For precise diagrams, and layout, please refer to the original PDF.
MC74F112 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The MC74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state cha...
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JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH.
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MC74F112 Datasheet
